Shuhan Liu (Stanford)- MIDDAS: Memory Integration and Data Dis-Aggregation
Abstract: Since the invention of the integrated circuit (IC) in 1958, the integration of exponentially more devices onto a single chip has transformed computing—yet memory remains largely separated from logic, creating “memory wall” that is the bottleneck of computing systems. Recent advances in memory research have introduced a variety of new technologies. Instead of expecting new memory devices to replace existing ones, we must embrace the integration of diverse memory types as a flexible toolkit for system designers. MIDDAS envisions a future where massive, diverse memories are physically integrated yet functionally store disaggregated data, enabled by holistic co-design from device to software. At the device level, MIDDAS encompasses a continuous spectrum of memory characteristics. This is exemplified by BRIDGE (Blended Retention-Indexed Diverse Gain cEll), a gain cell memory platform developed in my PhD research. The 2-transistor (2T) gain cell memory offers high density and CMOS integration compatibility. By leveraging oxide semiconductor (OS) transistors with ultra-low leakage current (< 1e-17 A/μm), BRIDGE expands the design space to support retention times ranging from microseconds to seconds, trading off speed as needed. Multiple gain cell configurations (Si-Si, OS-OS, OS-Si) and OS FET device designs enable fine-grained control over retention, speed, density, and power consumption. Crucially, BRIDGE introduces software-managed retention, transforming retention time from a hardware constraint into a programmable parameter for system-level power-performance-area-cost (PPAC) optimization. Furthermore, integrating gain cells with non-volatile memories (e.g., RRAM) unlocks synergistic system-level benefits through device-circuit-architecture co-design, embodying the “1+1>2” philosophy where diverse memory technologies collaboratively enhance system functionality through integration.
MIDDAS repositions memory as a scalable toolbox for computing in the AI era, capitalizing on the predictability of memory access, bridging device innovation with software demands.
Speakers
Shuhan Liu
Shuhan Liu is a final-year PhD candidate in Electrical Engineering at Stanford University, advised by Prof. H.-S. Philip Wong. She earned her Bachelor’s degree in Microelectronics from Peking University in 2020 and her Master’s degree in Electrical Engineering from Stanford in 2022. Her research interests lie in advanced memory technologies, monolithic 3D integration, and full-stack co-design, aiming to bridge device technologies and software through MIDAS (Memory Integration and Data Dis-Aggregation). Shuhan’s doctoral research centers on BRIDGE (Blended Retention-Indexed Diverse Gain cEll), an innovative on-chip memory solution that offers high density, low energy consumption, and high speed, with tunable retention. Her first author work on gain cell memory has been featured at leading conferences, including the International Electron Devices Meeting (IEDM) in 2023 and 2024, and the Symposium on VLSI Technology and Circuits (VLSI) in 2023 and 2024. These contributions have attracted coverage from major technology outlets such as IEEE Spectrum, Blocks&Files, and Techradar. Her extensive work on monolithic 3D integration for various memory technologies appears in multiple publications at IEDM (2021, 2024) and VLSI (2022). Her collaborative research with Prof. Zhenan Bao’s group on flexible electronics has resulted in high-impact publications in Nature (2024) and Science (2021). As of May 2025, Shuhan’s research has received over 780 citations, and she holds an H10-Index of 9 on Google Scholar. Her outstanding contributions have been recognized with several prestigious honors, including the 2024 IEEE Electron Devices Society PhD Fellowship and the 2024 IEEE Roger A. Haken Best Student Paper Award.
